Technical Field
The present invention relates to an alarm output circuit incorporated in an intelligent power module.
Background Art
An intelligent power module is such that a power semiconductor device, a gate drive circuit and protection circuit for the power semiconductor device, and the like, are integrated into a module. FIG. 4 shows a heretofore known example of an alarm output circuit incorporated in the intelligent power module.
Alarm factors in the intelligent power module include, for example, a drop in supply voltage (UV: Under Voltage) in agate drive circuit, overcurrent (OC: Over Current) of a power device such as an IGBT, and overheat (OH: Over Heat) and overvoltage (OV: Over Voltage) of the power device. Generations of the alarm factors are detected by respective unshown detection circuits. Detection signals output from the respective detection circuits are input into an OR circuit 1 via corresponding terminals T1, T2, T3, and T4.
(a) of FIG. 5 shows a detection signal relating to an alarm factor. The detection signal of H (High) level activates a latch timer 2 via the OR circuit 1. The latch timer 2, when no more alarm factor exists in a period in which the timer is in operation, cancels an output of the signal at a time-out point, but when some alarm factor remains at the time-out point, continues the output of the signal until the alarm factor is eliminated. The latch timer 2, when in operation, outputs a signal TM of H (High) level such as illustrated in (b) of FIG. 5.
The output signal TM of the latch timer 2 drives the gate of an output transistor 3. Consequently, the pulse signal of L (Low) level shown in (c) of FIG. 5 is output, as an alarm signal ALM, from an output terminal T5 pulled up by a resistor 4.
Meanwhile, PTL 1 discloses a device including individual pulse generating circuits, which generate pulse signals of different frequencies in response to generations of different alarm factors, and an OR circuit which inputs the pulse signals output from the respective pulse generators. According to the device, a generated alarm factor is identified from the frequency of a pulse signal output from the OR circuit.
Also, FIG. 2 of PTL 2 shows a heretofore known example having the same configuration as the alarm output circuit shown in FIG. 4. Further, FIG. 1 of PTL 2 discloses a technology wherein digital data indicating the presences and absences of generations of a plurality of alarm factors are input into a decoder, and generated alarm factors are identified by checking data output from the decoder against preset alarm factor detection data.
Furthermore, PTL 3 discloses a device including individual signal output circuits which generate pulse signals of different pulse widths in response to generations of different alarm factors. According to the device, when an alarm factor is generated, the alarm factor is identified based on the pulse width of a pulse signal output from a signal output circuit corresponding to the alarm factor.